Single-Cycle Read and Write
cycle
0
1
2
3
4
5
6
7
clk
cben[3:0]
ad[31:0]
framen
par
devseln
irdyn
trdyn
dp_start
dp_done
bar_select[2:0]
rd_cyc
rd_stb_out
rd_stb_in
6
ADDR
0
0
0
mem_add[15:0]
0000
0004
0008
000C
mem_data_in[31:0]
0
1
2
3
rd_sync
Figure 6-2 · Backend Read Cycle (RD_SYNC = 1)
Table 6-2 · Backend Initial Access Time Limits—
Delay Allowed from DP_START to RD_STB_IN or WR_BE_RDY (clock cycles)
Read
Family
RDSYNC = 0 RDSYNC = 1
Write
ProASIC
ProASIC3/E
PLUS
Axcelerator
RTAX-S
RTSX-S
SX-A
11
11
11
11
10
10
10
10
10
10
9
9
13
13
13
13
13
13
For write cycles, the backend indicates that it is ready to accept data by asserting WR_BE_RDY. The core then
indicates that it is ready to accept data from the PCI bus by asserting TRDYN. When the core receives data from the
PCI bus, it asserts the WR_BE_NOW strobes at the same time that the address and data are valid. For 32-bit PCI
transfers, four WR_BE_NOW signals are provided and used to validate each byte. Thus, if the PCI Master performs a
byte write, only one of the four write strobes will be active when the write occurs.
v4.0
53
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